Every year numerous students perform their university thesis research at our headquarters in Gothenburg.  
We are always open to discussing with students to find a suitable thesis topic.  You can find some examples below.
If you are interested please Connect with us and attach your CV and a list of completed courses.

Implementation of a SpaceWire RMAP Initiator IP Core
This thesis project involves the implementation and design of a digital Intellectual Property (IP) core that interfaces with the SpaceWire communication protocol, specifically focusing on the Remote Memory Access Protocol (RMAP). SpaceWire is extensively used in spacecraft avionics for high-speed data transfer. The IP core will act as an initiator, providing a memory-mapped area where read and write operations are translated into RMAP commands, effectively creating a communication bridge between two systems. The research will cover the entire development lifecycle including design, simulation, implementation, and validation of the IP core. The outcome is expected to facilitate more efficient data handling and improve interoperability in spacecraft systems.

Development of a Technical Report Generation Tool Using Language Models
This thesis aims to design and develop a tool for generating technical reports using large language models (LLMs) that are trained on existing technical documents. The project will involve the collection and curation of a diverse dataset of technical reports to train a model capable of understanding and generating similar content. The focus will be on creating a user-friendly tool that automates the generation of new reports, potentially saving significant time and resources in technical fields. Evaluation will include the accuracy and relevance of the generated reports, as well as the tool's adaptability to different technical domains.

Support System Assistant Based on Machine Learning
The objective of this thesis is to develop a support system assistant that leverages machine learning to provide suggested solutions to technical support staff. This assistant will be trained on a comprehensive database of existing technical support interactions and solutions. The project will explore both in-house developed models and external machine learning services to determine the most effective approach. The assistant's performance will be evaluated based on its accuracy in problem recognition and the relevancy of its suggested solutions. The project will also assess the system’s impact on the efficiency and effectiveness of the support staff's responses to user queries.

Benchmarks for machine learning applications
Machine learning applications are of high interest in future microprocessors for space applications. They can be executed on a wide variety of hardware and a trade-off will need to be done between dedicated hardware, e.g. in form of neural network accelerator IP, and running on general purpose processors. To support the trade-off, benchmarks suitable for machine learning applications are needed.
The thesis will survey the market for suitable benchmarks for machine learning applications and suggest a suite to run to support the future 16-core RISC-V based GR7xV microprocessor architecture design. A performance comparison between running the benchmarks in a dedicated accelerator for machine learning applications as well as on a general purpose processor, with and without vector support, will be done. To complete the trade-off, other aspects like resource utilization, should be considered. To achieve the goal, the selected benchmarks will be ported to the NOEL-V RISC-V processor as well as implemented on the machine learning accelerator IP.

On-chip interconnect comparison
Frontgrade Gaisler's microprocessors have traditionally been based on an AMBA AHB on-chip bus for the main interconnect. For the upcoming 16-core RISC-V based GR7xV microprocessor a new architecture is envisioned and for this a new on-chip interconnect is needed. The thesis will study different interconnect topologies and propose one for implementation. The thesis will furthermore propose a method to compare the performance of the new interconnect with a baseline AHB based system. A system-on-chip based on the chosen interconnect will be implemented and the performance in terms of bandwidth and latency will be measured and compared to the baseline.

High-performance system-in-package RISC-V processor for space applications
Combining several different semiconductor die into the same chip package, called System-In-Package, is increasingly common. This research effort involves an in-depth exploration of various technologies for multi-die packaging and Die-to-Die interconnect to identify the most fitting options for space applications. The secondary part will be related to architectural design, combining multiple chiplets like processors, accelerators, IO, and possibly High Bandwidth Memory in a unified chip package.

Benchmarks for the radiation testing of system-on-chip and microcontroller devices
Benchmarks have been used to compare different data processing devices. They are useful for determining how changes to technology, architecture, or compiler options affect a device's performance. In the Space sector, benchmarks are also useful for evaluating how a device performs under the influence of radiation effects.
The goal of this thesis is to research, propose, and integrate new test software applications into our existing benchmark suite. The applications could range from simple test codes to stress-specific hardware blocks of a device to complex AI-related and high-speed communication applications.
Depending on the schedule, the candidate may have the opportunity to follow a real radiation test campaign at a particle accelerator in Europe, having her/his code executed in the device under test.

Programmable protocol built on top of WizardLink interfaces
WizardLink is a family of transceivers used to send data over high-speed serial links. WizardLink has been commonly used in space missions as a simpler alternative to SpaceFibre. The goal of this thesis is to build an existing or a custom protocol using the existing WizardLink IP core and compare the performance with similar protocols such as SpaceFibre, both in terms of speed and packet loss rate.

Benchmarking the LEON5 & NOEL-V processors against on-board data handling benchmarks
OBPMark (On-Board Processing Benchmarks) is a set of computational performance benchmarks developed specifically for spacecraft on-board data processing applications. The thesis will explore the performance of the LEON5 & NOEL-V against the OBPMark benchmarks, also measuring the performance impacts of the fault tolerant features of the two processors.

Investigating advanced functionalities for monitoring cutting-edge FPGAs designed for space applications
This research focuses on the exploration of advanced features relevant to supervising Field Programmable Gate Arrays (FPGAs) through the Frontgrade Gaisler's GRSCRUB IP. The key objectives include:

• Conduct an exploratory work of state-of-the-art SRAM-based FPGA families tailored for space applications, assessing their relevance and suitability for external supervision
• Investigate strategies aimed at boosting performance, such as optimizing memory accesses and enhancing parallel processing capabilities
• Explore security boot mechanisms to ensure robust security features in the context of FPGA applications for space.

Development of a Single Event Effect Criticality Analysis (SEECA) flow for ASIC and FPGA designs
SEECA is a methodology (a tool) to identify the impact of Single Event Effects (SEE) on the availability and reliability of a space mission, system, subsystem, or component. The goal of this thesis is to develop a flow that extracts information from the netlist of a hardware design and correlates it with data from the target technology to build up a functional analysis and criticality classification of SEE on the system. The expected outcome of the work is a tool that can help hardware designs, during their entire development cycle, to predict and later validate with tests their performance against radiation effects.

Harnessing Artificial Intelligence for enhanced real-time data analysis
The goal of this work is to design an advanced real-time data analysis tool tailored for integration with radiation effects test  software. This tool shall efficiently receive, process, and present data through real-time graphs, with the added potential of  integrating an artificial intelligence engine to elevate its analytical capabilities.

In addition to the listed topics, we continuously add thesis projects within embedded software and ASIC/FPGA development. Do not hesitate to contact us for further discussions.