Every year numerous students perform their university thesis research at our headquarters in Gothenburg.  
We are always open to discussing with students to find a suitable thesis topic.  You can find some examples below.
If you are interested please Connect with us and attach your CV and a list of completed courses.

RISC-V cryptography extension application evaluation
The RISC-V Cryptography extensions allow to significantly facilitate implementation of secure and fast cryptography in RISC-V-based systems, through a set of scalar RISC-V instruction targeting cryptography.

This master thesis will survey the RISC-V Cryptography extensions and identify potential ways of using them in a system. A relevant security demonstration application of reasonable complexity will be selected and implemented using the cryptography instructions. The ease-of-use will be assessed and the cryptographic performance measured.

Predictive Memory Prefetch to cache subsystem
Cache prefetching for processors is a technique to improve processor performance by bringing instructions and data to the processor cache before they are needed by the processor, thus eliminating cache misses and increasing the overall performance. Potential caveats with prefetching are inefficient use of memory bandwidth, large variations depending on the applications, and that data access is generally more difficult to predict than instructions.

This master thesis will survey different Cache Prefetch approaches in software as well as hardware, and estimate the expected performance increase of the most interesting schemes. The possibility to select between more than one scheme depending on application shall also be assessed. A suitable cache prefetch scheme shall be selected, implemented and the performance impact measured, ideally also for a multi-core system which has memory bandwidth constraints.

Coherent on-chip architecture evaluation
Hardware support for cache coherency is an important feature in multi-core microprocessors. Frontgrade Gaisler has traditionally solved the problem by connecting all processor cores to a shared AMBA AHB and write-through caches together with bus snooping to detect memory updates. To improve performance in upcoming systems and allow for dividing the coherent subsystem into multiple subsystems, a more advanced coherency mechanism is needed. These coherency mechanisms come at the expense of overhead in terms of bandwidth or resources. Frontgrade Gaisler in collaboration with Chalmers is currently developing a proof-of-concept design based on an AMBA CHI based network-on-chip to replace a traditional shared AMBA AHB architecture. In this system the coherency traffic is expected to add a communication overhead to the interconnect.

The thesis will explore coherency mechanisms and propose evaluation methods for a coherent multi-core system. An evaluation suite will be set up either by reusing already existing benchmarks or by creating traffic generating VHDL IP cores or software and then applied to a traditional system based on a shared AMBA AHB to establish a baseline performance. The evaluation criteria will then be applied to a more advanced coherent architecture, such as an AMBA CHI based network-on-chip to compare the performance of the two systems.

Implementation of a SpaceWire RMAP Initiator IP Core
This thesis project involves the implementation and design of a digital Intellectual Property (IP) core that interfaces with the SpaceWire communication protocol, specifically focusing on the Remote Memory Access Protocol (RMAP). SpaceWire is extensively used in spacecraft avionics for high-speed data transfer. The IP core will act as an initiator, providing a memory-mapped area where read and write operations are translated into RMAP commands, effectively creating a communication bridge between two systems. The research will cover the entire development lifecycle including design, simulation, implementation, and validation of the IP core. The outcome is expected to facilitate more efficient data handling and improve interoperability in spacecraft systems.

Development of a Technical Report Generation Tool Using Language Models
This thesis aims to design and develop a tool for generating technical reports using large language models (LLMs) that are trained on existing technical documents. The project will involve the collection and curation of a diverse dataset of technical reports to train a model capable of understanding and generating similar content. The focus will be on creating a user-friendly tool that automates the generation of new reports, potentially saving significant time and resources in technical fields. Evaluation will include the accuracy and relevance of the generated reports, as well as the tool's adaptability to different technical domains.

Support System Assistant Based on Machine Learning
The objective of this thesis is to develop a support system assistant that leverages machine learning to provide suggested solutions to technical support staff. This assistant will be trained on a comprehensive database of existing technical support interactions and solutions. The project will explore both in-house developed models and external machine learning services to determine the most effective approach. The assistant's performance will be evaluated based on its accuracy in problem recognition and the relevancy of its suggested solutions. The project will also assess the system’s impact on the efficiency and effectiveness of the support staff's responses to user queries.

Benchmarks for machine learning applications
Machine learning applications are of high interest in future microprocessors for space applications. They can be executed on a wide variety of hardware and a trade-off will need to be done between dedicated hardware, e.g. in form of neural network accelerator IP, and running on general purpose processors. To support the trade-off, benchmarks suitable for machine learning applications are needed.
The thesis will survey the market for suitable benchmarks for machine learning applications and suggest a suite to run to support the future 16-core RISC-V based GR7xV microprocessor architecture design. A performance comparison between running the benchmarks in a dedicated accelerator for machine learning applications as well as on a general purpose processor, with and without vector support, will be done. To complete the trade-off, other aspects like resource utilization, should be considered. To achieve the goal, the selected benchmarks will be ported to the NOEL-V RISC-V processor as well as implemented on the machine learning accelerator IP.

Benchmarks for the radiation testing of system-on-chip and microcontroller devices
Benchmarks have been used to compare different data processing devices. They are useful for determining how changes to technology, architecture, or compiler options affect a device's performance. In the Space sector, benchmarks are also useful for evaluating how a device performs under the influence of radiation effects.
The goal of this thesis is to research, propose, and integrate new test software applications into our existing benchmark suite. The applications could range from simple test codes to stress-specific hardware blocks of a device to complex AI-related and high-speed communication applications.
Depending on the schedule, the candidate may have the opportunity to follow a real radiation test campaign at a particle accelerator in Europe, having her/his code executed in the device under test. 

Benchmarking the LEON5 & NOEL-V processors against on-board data handling benchmarks
OBPMark (On-Board Processing Benchmarks) is a set of computational performance benchmarks developed specifically for spacecraft on-board data processing applications. The thesis will explore the performance of the LEON5 & NOEL-V against the OBPMark benchmarks, also measuring the performance impacts of the fault tolerant features of the two processors.

Harnessing Artificial Intelligence for enhanced real-time data analysis
The goal of this work is to design an advanced real-time data analysis tool tailored for integration with radiation effects test  software. This tool shall efficiently receive, process, and present data through real-time graphs, with the added potential of  integrating an artificial intelligence engine to elevate its analytical capabilities.

In addition to the listed topics, we continuously add thesis projects within embedded software and ASIC/FPGA development. Do not hesitate to contact us for further discussions.